Onur Mutlu - Biography#
Onur Mutlu earned his dual Bachelor of Science degrees in Computer Engineering and Psychology from the University of Michigan, and his Master's and PhD in Computer Engineering from the University of Texas at Austin. During his PhD, he invented the Efficient Runahead Execution technique for tolerating long memory latencies in modern processors, variants of which are implemented in commercial microprocessors (e.g., IBM POWER6).
In 2006, he joined Microsoft Research to start the Computer Architecture Group. He conducted seminal research into memory systems for multi-core processors. His research into memory controllers spearheaded a fresh research area in computer architecture, which continues to thrive. Variants of his Parallelism-Aware Batch Scheduler [Mutlu+, ISCA'08] are implemented in memory controllers designed by Samsung.
In 2009, he moved to Carnegie Mellon University. He continued attacking the "memory problem" from all angles, with impact on both major academic research directions and commercial products. He advocated and analyzed the use of Phase Change Memory technology as part of the main memory of a computing system [Lee+, ISCA'09], starting a new area in computer architecture: how to enable/exploit emerging memory technologies. This work is considered a precursor of 3D XPoint by Intel. His work in flash memory reliability, starting with [Cai+, DATE'12], uncovered new error mechanisms, provided precious experimental data, and greatly improved flash memory lifetime. These works are regarded as prime resources for educating engineers in leading memory companies, Samsung, SK Hynix, Seagate, Sandisk, Micron, Toshiba. His work on key DRAM challenges (reliability, latency, energy, refresh, scaling) ignited substantial academic research and influenced industry directions. For example, his Subarray-Level Parallelism work [Kim+, ISCA'12] is advocated by Intel and Samsung to be in future DRAM standards.
In 2014, he discovered the RowHammer problem [Kim+, ISCA'14], a failure mechanism affecting most real DRAM chips. This work shook the fundamentals of systems security: Google and many others demonstrated attacks that exploit RowHammer to take over an otherwise-secure system. RowHammer is the first example of a hardware failure mechanism that causes a practical and widespread system security vulnerability. It continues to have widespread impact on systems, security, software, and hardware communities, both academic and industrial: e.g., it caused a new Hammer Test to be included in standard memory test programs, and Apple cited the work in its critical security release that introduced a hardware patch to mitigate RowHammer.
For his contributions, he received the endowed Strecker Early Career Professorship at Carnegie Mellon (2013), the first IEEE Computer Society Young Computer Architect Award (2011), the first Intel Early Career Faculty Award (2012), and the Ladd Research Award from CMU (2012). 11 of his papers were chosen as Top Picks by IEEE Micro, and more than 14 received Best Paper recognitions. He received numerous Faculty Awards from Facebook, Google, HP, Huawei, IBM, Intel, Microsoft, NSF, VMware.
He spent significant time in industry, enabling technology transfer of his ideas. He was with Intel (Summer'01-'03 and '12) and AMD (Summer'04-'05), researching novel microprocessor designs, and with VMware (Feb-Sep'16) and Google (May-Sep'16), exploring new memory architectures. He continues to collaborate with industry on both fundamental and cutting-edge technology issues.
In September 2015, he was appointed Full Professor of Computer Science at ETH Zurich, where he started in May 2016. He continues to thrive on research, education, and service for the community. His computer architecture course videos/materials and his group's research artifacts are freely available online, and used by many educators, researchers and practitioners worldwide. He was elected an ACM Fellow in 2017, for "contributions to computer architecture research, especially in memory systems."
