Per Stenström#
Short laudatio by Mateo Valero#
Per Stenstrom is a world-renowned expert in computer architecture and one of the most influential researchers in computer architecture in Europe. His contributions cover a broad range of topics in computer architecture with the main theme of enabling a high computational performance. He has done numerous contributions over the years especially in the areas of memory systems for multiprocessors and embedded time-critical systems and to architectural support for exploiting parallelism.
Memory system design is critical to the performance and cost-effectiveness of computers. However, technology trends make the relative speed between processing and memory access higher. Further, in parallel computers, that are now mainstream, multiple processors share the same memory system which makes the speed mismatch between memory and processors more problematic.
Per Stenstrom’s has contributed numerous concepts in multiprocessor memory systems to increase the efficiency of memory access by proposing novel designs of cache coherence protocols, by exploiting relaxed memory consistency models, and by using speculative techniques such as producer-induced updates and consumer-induced pre-fetching. His work on this topic has inspired researchers to follow in his footsteps. He has also proposed novel concepts using compression to significantly increase memory resource utilization.
Many embedded systems have stringent time requirements. At the same time, many architectural concepts such as caches and out-of-order execution jeopardize timing predictability. Per Stenstrom‘s work on establishment of tight and safe bounds on the execution time in systems using caches and out-of-order instruction execution has been influential to the literature on WCET (worst-case execution time) analysis methods.
Now that parallel computers have become mainstream and important issue is how to enrich the hardware/software interface with primitives to make it easier to extract parallelism. Per Stenstrom has contributed to this area with novel concepts for thread-level speculative execution and transactional memory to allow parallelism to be unlocked with low programming effort .
Finally, Per Stenstrom has offered extensive services to the scientific community by organizing multiple conferences, participation in technical program communities more than 50 times and as general and program chair multiple times. He has delivered several keynote speeches at prestigious conferences in the field. He is acting as editor regularly and has devoted a significant amount of his time to building the European HiPEAC Network of Excellence, one of very few successful such instruments that have put together the community in computer architecture and compilers in Europe to focus the community’s efforts on the problems of the highest scientific relevance.
He is a Fellow of the IEEE and the ACM and a member oft he Royal Swedish Academy of Engineering Sciences.
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