Donatella Sciuto - Selected Publications#

R. Cattaneo, G. Natale, C. Sicignano, D. Sciuto, and M. Santambrogio. “On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach”, ACM Trans. Archit. Code Optim. 12, 4, Article 53 (January 2016), 26 pages. DOI: Citations 37

Iterative Stencil Loops (ISLs) are a specific class of algorithms of great importance for their presence in many industrial and scientific computing applications, such as in numerical methods for solving partial differential equation used for instance for random number generation and error correction. The computationally intensive nature of those algorithms created the need for solutions to efficiently implement them in order to save both execution time and energy. However, most of these works are focused on aggressive compile time optimization, cache locality optimization, and parallelism extraction for the multicore/multiprocessor domain. Donatella saw this as an opportunity to propose a methodology to systematically design power-efficient hardware accelerators for the optimal execution of ISLs on a multi-FPGA system. Furthermore, the proposed solution focused on the design and exploitation of a specific domain architecture to further exploit the regular structure of Iterative Stencil Loops, specifically with the goal of improving power efficiency

A. Nacci, V. Rana, B. Balaji, P. Spoletini, R. Gupta, D.Sciuto, Y. Agarwal, 2018). BuildingRules: A Trigger-Action--Based System to Manage Complex Commercial Buildings. ACM Transactions on Cyber-Physical Systems, vol. 2, p. 1-22, ISSN: 2378-962X, doi: 10.1145/3185500 Citations: 37

Modern Building Management Systems (BMSs) have been designed to automate the behavior of complex buildings, but unfortunately they do not allow occupants to customize it according to their preferences, and only the facility manager is in charge of setting the building policies. To overcome this limitation, Sciuto and coworkers created BuildingRules, a trigger-action programming-based system that aims to provide occupants of commercial buildings with the possibility of specifying the characteristics of their office environment through an intuitive interface. Trigger-action programming is intuitive to use and has been shown to be effective in meeting user requirements in home environments. BuildingRules backend is based on RESTful web services so it can connect to various BMSs and scale well with large number of buildings. The Authors have tested our system with 23 users across 17 days in a virtual office building, and the results we have collected prove the effectiveness and the scalability of BuildingRules.

A.Corna, L. Fontana, A. A. Nacci and D. Sciuto, Occupancy detection via iBeacon on Android devices for smart building management, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), DOI: 10.7873/DATE.2015.0753, Citations: 91

This paper has shown the major challenges in occupancy detection: the signal stabilization, the classification algorithms and the energy efficiency on the mobile device used to sense the environment. On the classification algorithms side, the Authors have increased the accuracy from 84% to 94%. On the application energy efficiency, proposing an alternative communication pattern via Bluetooth, has obtained a 15% improvement. This work has been the basis for the patent: Metodo per la localizzazione di un dispositivo all'interno di un’area, Applicant: Politecnico di Milano, Application number: 102017000142307 11/12/2017

G. Beltrame, D. Sciuto, C. Silvano, “Multi-Accuracy Power and Performance Transaction-Level Modeling”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume 26, Issue 10, pp. 1830-1842, Oct. 2007. Citations 55

The work has been invented and propelled by Donatella Sciuto, who was one of the first researchers to look into Transaction Level Modeling, having been interested in system-level design and specification for years. She has worked closely with her PhD student Giovanni Beltrame and they were the first to define a technique for modeling and simulation that extends TLM to sup- port multi-accuracy models and power estimation. This approach provides different combinations of power and performance models, and the switching of model accuracy during simulation, allowing the designer to trade-off between simulation accuracy and speed at runtime. This is particularly useful during the exploration phase of a design, when the designer changes the features or the parameters of the design, trying to satisfy its constraints. This work has been included also in an internal development proprietary tool by STMicroelectronics.

F. Ferrandi, P. Lanzi, C. Pilato, D. Sciuto, A. Tumeo (2010). “Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems”. IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol. 29, p. 911-924, ISSN: 0278-0070, doi: 10.1109/TCAD.2010.2048354 Citations: 188

To exploit the power of modern heterogeneous multiprocessor embedded platforms on partitioned applications, the designer usually needs to efficiently map and schedule all the tasks and the communications of the application, respecting the constraints imposed by the target architecture. Since the problem is heavily constrained, common methods used to explore such design space usually fail, obtaining low-quality solutions. The key contribution of Donatella's work is to leverage the concept of an ant colony optimization (ACO) heuristic that, given a model of the target architecture and the application, efficiently executes both scheduling and mapping to optimize the application performance. The results of this work are surprisingly good when compared our approach with several other heuristics, including simulated annealing, tabu search, and genetic algorithms, on the performance to reach the optimum value and on the potential to explore the design space.

F. Sironi, D. Bartolini, S. Campanoni, F. Cancare, H. Hoffmann, D. Sciuto, and M. Santambrogio. 2012. “Metronome: operating system level performance management via self-adaptive computing”, In Proceedings of the 49th Annual Design Automation Conference (DAC ’12). Association for Computing Machinery, New York, NY, USA, 856–865. DOI: Citations: 65

The demands in terms of computing performance, functionality, reliability, and availability has grown exponentially, raising the overall complexity of the hardware/software execution stack. Hardware developers multiply the amount of resources making them more and more heterogeneous and posing an ever–increasing burden on both system and application developers. This is even more evident in the embedded systems domain, where capabilities may present huge variations among different system configurations. The Metronome framework has been proposed to overcome these challenges. Metronome is a self-adaptive solution constituting an implementation of the ODA control loop to enhance commodity operating systems. Furthermore the reference implementation of Metronome is publicly available as free software and widely used.

G. Beltrame, L. Fossati and D. Sciuto, “ReSP: “A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume 28, Issue 12, pp. 1857-1869, Dec. 2009. Citations: 126

The paper introduces a transaction-level multiprocessor simulation platform based on the integration of SystemC and Python. ReSP exploits the concept of reflection, enabling the integration of SystemC components without source-code modifications and providing full observability of their internal state. ReSP offers fine-grained simulation control and supports the evaluation of different hardware/software configurations of a given application, enabling complete design space exploration. ReSP allows the evaluation of real-time applications on high-level hardware models since it provides the transparent emulation of POSIX-compliant Real-Time Operating Systems (RTOS) primitives. The results show that ReSP can be successfully used to analyze and explore concurrent and reconfigurable applications even at very early development stages, because of its accuracy and faster execution time. The tool is available open source at:

R. Cordone, F. Redaelli, M.A. Redaelli, M.Santambrogio, D. Sciuto, “Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume 28, Issue 5, pp. 662-675, May 2009. DOI: 10.1109/TCAD.2009.2015739 Citations: 58

This work has been one of the first in the scientific community on reconfigurable systems to define a systematic design methodology allowing the designer to start form a high-level specification of the system and guiding him/her to the generation of the necessary bitstreams, software and hardware components providing a run-time dynamically partially reconfigurable system on FPGAs. This has generated a strong interest from the FPGA vendors, since it complements commercial software by enabling the exploitation of dynamic reconfigurability provided by the device.

D. Bartolini, F. Sironi, D. Sciuto, and M. Santambrogio. “Automated Fine-Grained CPU Provisioning for Virtual Machines”, ACM Trans. Archit. Code Optim. 11, 3, Article 27 (October 2014), 25 pages. DOI: Citations: 18

Infrastructure as a Service clouds had enabled business flexibility with a pay-as-you-go model for computation. Within this model, the interest of users was minimizing business costs for executing a given workload with the desired performance, while the interest of vendors is optimizing infrastructure utilization, so as to minimize the total cost of ownership, without breaking service level objectives. What was lacking in virtualization infrastructures where tools to easily fulfill these interests: users need to manually determine the amount of resources to rent; providers have to be conservative when consolidating workloads on multicore-powered host nodes to reduce total cost of ownership, since colocation can lead to unexpected performance degradation. The Authors conceived AutoPro, a system able to automatically size and enforce allocations of a contended resource based on user-defined, application-level performance requirements would be a valuable tool to help more easily meet users’ and providers’ interests. This worked filled an important gap in this technology.

M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, “An Instruction-Level Energy Model for Embedded VLIW Architectures”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume 21, Issue 9 , pp. 998-1010, Sep. 2002. DOI: 10.1109/TCAD.2002.801105 Citations: 82

This paper provides us with a key reference on power estimation. Namely it provides us with an efficient method for system-level power estimation of processor architectures with good accuracy, for design space exploration purposes. Thus its implementation has been widely used within the community.

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