Subhasish Mitra - Selected Publications#

H-index: 69 (Google Scholar). Citations: 18,631 (Google Scholar)
H-index: 40 (Web of Science), Citations: 5507 (Web of Science)

Nano-electronic systems (NanoSystems):

1. M. Shulaker, G. Hills, N. Patil, H. Wei, H. Chen, H.-S.P. Wong and S. Mitra, “Carbon Nanotube Computer,” Nature, Vol. 501, Issue 7468, pp. 526-530, 2013 (Nature Cover Feature). (891 citations)

2. M. Shulaker, G. Hills, R. Park, R.T. Howe, K. Saraswat, H.-S.P. Wong and S. Mitra, “Three-dimensional Integration of Nanotechnologies for Computing and Data Storage on a Single Chip,” Nature, Vol. 547, Issue 7661, pp. 74-78, 2017. (Special News and Views feature by Nature). (299 citations)

3. M. Aly, M. Gao, G. Hills, C-S Lee, G. Pitner, M. Shulaker, T. Wu, M. Asheghi, J. Bokor, F. Franchetti, K. Goodson, C. Kozyrakis, I. Markov, K. Olukotun, L. Pileggi, E. Pop, J. Rabaey, C. Ré, H.-S.P. Wong and S. Mitra, “Energy-Efficient Abundant-Data Computing: The N3XT 1,000X,” IEEE Computer, Special Issue on Rebooting Computing, Vol. 48, Issue 12, pp. 24-33, Dec. 2015. (165 citations)

[1, 2, 3] represent the world’s first NanoSystems amongst all promising emerging nanotechnologies for high-performance and highly energy-efficient digital systems.

Carbon nanotubes (CNTs) are a beyond-silicon nanotechnology for fast and low-energy digital logic. Stubborn imperfections inherent in CNTs stalled progress for over a decade – it was not possible to realize robust CNT-based systems. Prof. Mitra and his team created a new approach that overcomes these obstacles and built the first CNT microprocessor [1] – the first system realized using beyond-silicon nanotechnology (not just CNTs).

[2, 3] create new monolithic three-dimensional (3D) architectures uniquely enabled by beyond-silicon nanotechnologies (CNT digital logic, resistive RAM memory, CNT sensing) with large system-level benefits. [2] demonstrates the first 3D NanoSystem hardware which senses and captures massive data, stores it in 3D layers, and performs in-situ machine learning – the largest and most complex of such revolutionary architectures.

[1-3] are profoundly transforming the next-generation electronics landscape. They form the basis for DARPA’s 3DSoC program (the single largest DARPA program awarded to academia), which has already established these technologies at the commercial SkyWater Technology Foundry. While not yet public, Analog Devices (ADI, a Fortune 500 hardware company) has recently established these technologies within their commercial manufacturing facility – a joint effort between ADI's Healthcare Business Unit, Manufacturing Unit, and Advanced Development Unit. Recognitions of the work in [1 -3] include Nature Cover, Best Paper Awards at major venues, NSF Highlight to the US Congress, Special recognition by SEMI (Award 2 in 1.14), and Dissertation Awards for Prof. Mitra’s Ph.D. students.

Testing of electronic systems:

4. S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” IEEE Intl. Test Conf., pp. 311-320, 2002.

5. S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique,” IEEE Trans. CAD, Vol. 23, Issue 3, pp. 421-432, March 2004 (Expanded version of [4])

(491 citations total for [4] and [5])

X-Compact [4, 5] has proven essential to cost-effective manufacturing and high-quality testing of almost all contemporary electronic systems today, enabling billions of dollars in cost savings across the industry. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation (EDA) tools, e.g., Synopsys, Cadence. In addition to paper awards, X-Compact received ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in EDA (a test of time honor, Award 5 in 1.14) and Intel's highest corporate honor, the Intel Achievement Award (IAA, Award 12 in 1.14).

Resilient electronic systems:

6. S. Mitra, N. Seifert, M. Zhang, Q. Shi and K.S. Kim, “Robust System Design with Built-In Soft Error Resilience,” IEEE Computer, Vol. 38, Issue 2, pp. 43-52, Feb. 2005.

7. M. Zhang, S. Mitra, TM Mak, N. Seifert, Q. Shi, K.S. Kim, N. Shanbhag, N. Wang and S.J. Patel, “Sequential Element Design with Built-In-Soft-Error-Resilience,” IEEE Trans. VLSI, 2006, Vol. 14, Issue 12, pp. 1368-1378, Dec. 2006 (Expanded version of [3]).

(997 citations total for [3] and [4])

8. M. Agarwal, B. Paul, M. Zhang and S. Mitra, “Circuit Failure Prediction and Its Application to Transistor Aging,” IEEE VLSI Test Symp., pp. 277-286, 2007. (564 citations)

9. Y. Li, S. Makar and S. Mitra, “CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns,” IEEE/ ACM Design Automation and Test in Europe, Munich, Germany, pp. 885-890, 2008. (191 citations)

[6 - 9] have spurred significant research and industrial practice on resilient electronic systems, from deeply embedded systems to cloud computing and supercomputers, that must tolerate hardware errors during their operation.
[6, 7] and their extensions solve the critical challenge of soft errors during system operation that cause unexpected data corruption or expensive downtimes. Radiation beam results by TSMC, Intel, Cisco, Broadcom, Marvell, Boeing and many others have verified that these techniques improve soft error rates by 3 to 5 orders of magnitude all the way to sub-10nm feature sizes.

[8] formulates the concept of circuit failure prediction for signaling impending circuit failures before errors occur, with extensive follow-on activities in industry and academia – its adoption is growing rapidly, in markets ranging from cloud computing to automotive systems (e.g., Google, Proteantecs), for predictive health monitoring of electronic systems throughout their lifecycle.

CASP [9] enables a system to predict and detect hard failures by testing itself concurrently during normal operation. CASP and its derivatives have been implemented in major products (e.g., Intel, Nvidia, Renesas, Texas Instruments and in Synopsys tools) for cloud computing and automotive ISO26262 automotive safety standard.

Approaches in [6 -9] received Best Paper Awards (including Ten Year Retrospective Most Influential Paper Award) at major venues, Intel’s Divisional Recognition Award (“for breakthrough soft error protection technology”), Dissertation Awards for Prof. Mitra’s Ph.D. students, Research Highlight by Intel Labs, and Highlight by DARPA (as one of three major results of its PERFECT program).

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